This is after power has been applied and the reset button has been pushed, which should leave the RC2014 is a consistent stable state. They are captured at 2v/1us per division and labelled according to the pin function.
100 MHZ CLOCK MINI ZED SERIAL
If you get this, then your RC2014 is working and executing code, so any problems are going to be serial related.įor completeness, the following traces are for each of the pins on the RC2014 expansion bus. This is the ASCII for “Z80 SBC By Grant Searle. When zoomed in at 200us/div you can see the individual pulses on the Tx line. If you probe the TX line and trigger from the reset line going high, you should see a burst of signal from the TX line just after releasing the reset button.įirst shot above is taken at 10ms/div. (If you have the 3.68Mhz Clock Module the frequency will obviously be different)
The image above shows the clock in yellow, 2v/50ns per division to give a 7.37Mhz clock 0-5v with a bit of overshoot. The clock on the RC2014 is a fairly simple design, so you won’t get a perfect square wave, but it should be reasonably square-ish with a clear distinction between 0v and 5v
The first thing to check for is a good clock signal. Although the screen shots that follow were taken on a 100Mhz 4 channel digital storage scope, even a basic 10Mhz 2 channel analog scope will be able to give you the same kind of info.
100 MHZ CLOCK MINI ZED HOW TO
I’ve made the assumption that you have a reasonable idea how your scope works, so will gloss over the details of how to set things up. the clock resources.If you have access to an oscilloscope then this can help greatly in troubleshooting a non-running RC2014. If you do the latter, the tools should handle the clock constraints for the generated clock.Īnother thing you could consider - is to look at some of the Xilinx TRD (technical reference designs) which use the oscillators on the board for various functions - and see how they wire/reference/MMCM/PLL/etc. You can either change that clock's frequency w/ I2C commands *or*, use the clock wizard to instantiate an MMCM/PLL to convert that clock to the target frequency you care about. IIRC, there is at least one variable-frequency Si570 clock oscillator you can use - it has a default frequency when the board is powered on.
100 MHZ CLOCK MINI ZED MANUAL
You will want to read the ZCU102 reference manual and look at the clock generators it provides. The timing analysis constraint has no bearing on the actual runtime frequency of the oscillator connected to a pin. It looks like ACLK is a top-level port and you need to tell the tools which package/pin the ACLK is coming from. This only creates the constraint for the clock to be used during timing analysis. tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.
launch_runs Tcl command), add this command to a. NOTE: When using the Vivado Runs infrastructure (e.g. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To correct this violation, specify all pin locations. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. Unconstrained Logical Port: 1 out of 17 logical ports have no user assigned specific location constraint (LOC). This resulted in an error like no user assigned specific location constraint (LOC): One thing I also tried (and failed to generate a bitstream) was to use tcl commands in the constraint file to generate the clock: create_clock -name ACLK -period 10
0 kommentar(er)
